RESPONSIBILITIES
- Integrate and verify IP blocks in SoC, and support physical implementation.
- Define SoC level specifications, architecture and operation scenario.
- Understand standard interface specification (e.g., PCIe) and chip operation scenario to configure IP blocks to be integrated into SoC.
- Performance analysis in chip top level (bus, memory bandwidth) simulation and FPGA prototyping.
MINIMUM QUALIFICATIONS
- Master's degree in Electrical Engineering, Computer Science or equivalent practical experience.
- 2+ years of industry experience in chip design, specializing in SoC integration and design automation
- Experience in RTL design and logic synthesis, verification, timing closure
PREFERRED QUALIFICATIONS
- Experience in high-speed connectivity IP (e.g., PCIe, USB, MIPI, etc) is a plus - Experience in video codec (decoder, encoder) is a plus
- Experience in interconnect, memory subsystem is a plus
CONTACT
- recruit@furiosa.ai