ML HW-SW Co-Design Silicon Tech Lead Manager

Snapshot At Google DeepMind, we value a unique culture where long-term ambitious research flourishes. We are seeking a highly motivated ML Silicon Tech Lead Manager to join our HW-SW co-design team. This is a hands-on role for a deeply technical expert who will also lead a high-impact team to drive advances in machine learning acceleration. About You GenAI at Google DeepMind prioritizes deeply technical leadership. We are looking for an individual who: Contributes as a Senior IC: You are expected to be a direct technical contributor, particularly during onboarding and within key workstreams. Acts as a Technical Anchor: You excel at aligning senior engineers who may have diverging technical directions. You are the person who reduces the feeling of "too many moving parts" by providing a cohesive architectural north star. Thrives in Ambiguity: You are flexible enough to change course when ideas don't work out and willing to "plug in" wherever the project needs the most senior technical support. The Role As a TLM, you will spend a significant portion of your time on technical execution while managing a multi-disciplinary team to evolve our ML accelerator designs in close collaboration with a paired ML software team. Key Responsibilities: Direct Technical Contribution (IC): Directly contribute to the codebase and technical strategy. IC focus can be one specific silicon engineering discipline, or spanning the program needs more broadly. Technical Team Leadership: Lead a small team of ML silicon engineers across logic design, physical design, interconnect, and power. Architectural Alignment: Drive team cohesion by synthesizing fragmented technical opinions into a single, high-quality execution plan. HW-SW Strategy: Partner closely with the ML software team to define requirements for next-generation ML accelerators. Execution Management: Oversee technical execution across a virtual team including Google-internal and external partners. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10+ years of experience in silicon architecture, design, validation, or product development. Proven track record of technical leadership and successfully delivering complex silicon projects (tape-outs) to production. Deep expertise in at least one core silicon discipline (e.g., RTL, PD, DV) and strong familiarity with the entire ASIC flow. Experience with managing cross-functional silicon projects, including schedule, scope, and execution, and also managing silicon vendors and other external partners. Preferred Qualifications: Master's or Ph.D. in a related field. Experience leading and managing teams across the full silicon development cycle, from RTL to bringup. Experience with high-performance compute IPs (e.g., GPUs, ML accelerators). Knowledge of high-performance and low-power architectures for ML acceleration. Excellent communication, and leadership skills.